1. Technical Field
The embodiments described herein relate to a clock generation circuit, and more particularly, to a multi-phase clock generation circuit.
2. Related Art
As memory system technologies are developed and as they advance forward, corresponding techniques for processing data at higher speeds are also needed. That is, techniques for transferring data at higher rates are needed to match those advances in memory system technologies. In order to process serial data at a high data transfer rate with a high-bandwidth, a pre-fetch scheme is employed in a semiconductor memory apparatus.
The pre-fetch scheme latches data input in series to process the data in parallel. In order to perform this type of pre-fetch scheme, a semiconductor memory apparatus must use clocks having different phases.
As generally known to those skilled in the art, a phase locked loop (PLL) is used to generate clocks having different phases, that is, multiple phase clocks. Unfortunately, this type of PLL circuit occupies a large area and consumes a great deal of current. Accordingly, this type of PLL circuit is mostly restricted to use in lower-power-operations. For this reason, recently, a phase interpolator has been mainly used which receives two clock signals to generate a clock obtained by interpolating a phase difference between the two clock signals.
In detail, the phase interpolator generates a new clock signal having a center phase between two input clock signals. Unfortunately, as the frequency of the clock signals have been steadily increasing, it is becoming more and more difficult to generate an appropriate clock signal that exhibits an exact phase. Accordingly, a phase offset may occur in each clock having a multi-phase which ends up in allowing a phase error to occur. As a result of a phase error, valid data section may be compromised, when data are transmitted in synchronization with the multi-phase clock that exhibits this type of phase error.